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submitted 3 months ago by cm0002@lemdro.id to c/riscv@programming.dev

The MIPS I8500 features a scalable multithreaded architecture with 4 threads per core and support for multi-cluster deployments, enabling up to 24 threads per cluster. It delivers ultra-low-latency, deterministic data movement with integrated security, ideal for orchestrating packet flows across accelerators and enabling intelligent communication between compute blocks, humans, and networks. Its energy-efficient design ensures optimal performance for edge AI workloads, while RVA23 profile readiness and support for Linux and Real-Time operating systems ensures software portability and ecosystem alignment.

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this post was submitted on 17 Oct 2025
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RISC-V

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RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

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