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Japan tried to build an operating system for the entire world, then the US government intervened (www.xda-developers.com)
submitted 3 days ago* by to c/technology@lemmy.world
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[–] 79 points 2 days ago (1 child)

Three CPUs with different architectures on one device sounds crazy. That's amazing.

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  • [–] 49 points 2 days ago (6 children)

    PS3 comes to mind

    Though in embedded, thats fairly normal.

    I've got a $1 linux embedded SoC that has a 64 bit riscv core, a 32 bit riscv core for running realtime stuff and a low power embedded 6502 on it too because why not.

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  • [–] 12 points 2 days ago (1 child)

    Yeah, RP2350 in Raspberry Pi Pico 2 also has 2 ARM cores and 2 RISC-V cores.

    Which reminds me, I purchased one a month ago to play around with as it has good documentation, yet I haven't used it once so far.

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  • [–] 7 points 2 days ago* (1 child)

    Its actually not seperate cores, they're RISCV or ARM, based on a switch. MilkV does that too with one of its chips. They're mostly the same architecturally, theres something like 10% that gets enabled/disabled with each ISA selection.

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  • [–] 9 points 2 days ago* (last edited 2 days ago) (1 child)

    But you can still run both at once. RP2350 datasheet

    From section 3.9 Arm/RISC-V architecture switching:

    There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions).

    From section 3.9.2. Mixed architecture combinations:

    The ARCHSEL register has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.

    Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing ldrex, strex instructions and a RISC-V processor performing amoadd.w instructions, for example

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  • [–] 5 points 2 days ago* (last edited 1 day ago) (1 child)

    Original Nintendo DS had two different ARM CPUs for DS games and the same CPU the GBA had for direct compatibility.

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  • [–] 5 points 2 days ago (1 child)

    The second CPU is the GBA CPU, but at twice the clockspeed (which can then downclock for GBA games). You're double-counting it and making it sound like the system had three.

    The 3DS is the real funny one, adding its own new CPU alongside both the DS and GBA CPUs. So that's actually three.

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  • [–] 1 point 2 days ago (1 child)

    OSX (now MacOS) was built and running on PowerPC and Intel for years before Intel Macs were released. I assume the same was true before they released the Apple silicon chips.

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  • [–] 7 points 2 days ago

    Yeah but they weren't running both in the same device at the same time.

    PPC -> Intel they just recompiled their OS and fixed it up for the x86 platform, then the same for Intel -> ARM

    They did not have a laptop with an x86 processor and a PPC at the same time.. though there are some hillariously bespoke accellerator cards from back in the day to do all sorts of strange things.

    That said, laptops are full of microcontrollers with firmware, lots of those will be atmega, st32, 6502 and the like. Things like a WLAN or WAN card will be a little ARM soc of some flavour.

    So it really depends on where you draw the line. If its executing the main workload, I'd say thats the CPU, everything else is a microcontroller enabling it to do that

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  • [+] -17 points 2 days ago (1 child)

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  • [–] 7 points 2 days ago (1 child)

    Haha look at this dumbass, he thinks being stupid is aspirational.

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  • [+] -15 points 2 days ago (1 child)

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