One of the key problems of learning VHDL at universities is that most teachers there are amazingly clueless about the language. Not only do you need a bit of a different mindset (you do not program, you define), but their knowledge of language and systems is stuck in the last century.

When I was a regular in a VHDL group on the site we don't mention here, we regularly had students who got taught techniques that are obsolete or at least deprecated since 1989.